#ifndef FH_QOS_GMAC_H_
#define FH_QOS_GMAC_H_


#define FH_GMAC_PHY_IP101G	0x02430C54
#define FH_GMAC_PHY_RTL8201	0x001CC816
#define FH_GMAC_PHY_TI83848	0xFFFFFFFF
#define FH_GMAC_PHY_INTERNAL 0x441400


// enum {
// 	GMAC_SPEED_10M,
// 	GMAC_SPEED_100M,
// };

enum {
	GMAC_DUPLEX_HALF,
	GMAC_DUPLEX_FULL,
};


enum {
	gmac_phyt_reg_basic_ctrl = 0,
	gmac_phyt_reg_basic_status = 1,
	gmac_phyt_reg_phy_id1 = 2,
	gmac_phyt_reg_phy_id2 = 3,
	gmac_phyt_rtl8201_rmii_mode = 16,
	gmac_phyt_ti83848_rmii_mode = 17,
	gmac_phyt_rtl8201_power_saving = 24,
	gmac_phyt_rtl8201_page_select = 31,
	gmac_phyt_ip101g_page_select = 20
};

struct dwcqos_dma_desc {
	u32	desc0;
	u32	desc1;
	u32	desc2;
	u32	desc3;
};


struct dw_qos_hw_feature{
	u32 feature0;
	u32 feature1;
	u32 feature2;

	u32 tx_fifo_size;
	u32 rx_fifo_size;
	//txq should == tx dma num.(ip required)
	u32 txq_num;
	u32 rxq_num;
	u32 tx_dma_num;
	u32 rx_dma_num;
	u32 tso_flag;
};



struct net_tx_queue {
	unsigned int irq_num;
	unsigned int id;
 
	void *p_raw_desc;
	struct dwcqos_dma_desc *p_descs;
	/* DMA Mapped Descriptor areas*/
	u32 descs_phy_base_addr;
	u32 descs_phy_tail_addr;
	u32 desc_size;
	u32 hw_queue_size;
	u32 desc_idx;
	u32 desc_xfer_max_size;
};


struct net_rx_queue {
	unsigned int irq_num;
	unsigned int id;

	void *p_raw_desc;
	struct dwcqos_dma_desc *p_descs;
	/* DMA Mapped Descriptor areas*/
	u32 descs_phy_base_addr;
	u32 descs_phy_tail_addr;
	u32 desc_size;
	u32 hw_queue_size;
	u32 desc_idx;
};

struct dw_qos
{
    void *regs;
	int id;
	unsigned char local_mac_address[6];
	int phy_id;
	int phy_addr;
	int duplex;	
	int speed;

	struct dw_qos_hw_feature hw_fea;
	struct net_tx_queue *tx_queue;
	struct net_rx_queue *rx_queue;
	int phy_interface;
	struct mii_dev *p_mii_bus;
	struct phy_driver *p_phy_dri;
	struct phy_device *p_phy_dev;
	unsigned int active_queue_index;
	struct gmac_plat_info *p_plat;
	//bind to net dev
	struct eth_device* ndev;
};

struct dwcqos_dma_desc  *get_tx_active_desc(struct dw_qos* pGmac, u32 q_no);
void dwcqos_dma_chan_set_mss(struct dw_qos* pGmac, u32 q_no, u32 val);
void fh_qos_mac_send_with_desc(struct eth_device* dev, struct dwcqos_dma_desc  *p_tx_desc);
int fh_qos_mac_scan_dll_init(struct dw_qos *gmac, uchar **pp_rx_packets, u32 packets_size, u32 spd);
int fh_qos_mac_receive_with_buf(struct eth_device* dev, u8 *rx_buf, u32 rx_cnt);
int fh_qos_mac_send(struct eth_device* dev, void *packet, int length);
void dwcqos_set_hw_mac_filter(struct dw_qos* pGmac, u32 filter);
// #ifndef CONFIG_EMULATION
// #define CONFIG_EMULATION
// #endif

#endif
